1. Field of the Invention
The present invention relates to a test apparatus and a test method. Particularly, the present invention relates to a test apparatus and a test method that test a plurality of device under tests.
2. Related Art
Generally, a test apparatus that tests a semiconductor device such as a flash memory. The test apparatus performs a functional test by applying test signals to DUT (Device Under Test) and comparing a result signal outputted from the DUT in response to the test signal with a reference voltage to determine pass/fail of the DUT based on whether the comparison result is corresponding to an expected value. Here, testing a flash memory, the test apparatus has to read as a test pattern an operational parameter of the flash memory, such as a setting value of a writing voltage to a memory cell as disclosed, for example, in Japanese Patent Application Publication No. 2001-93296.
Testing a plurality of flash memories in parallel, the test apparatus has to individually set the test pattern for each DUT because the characteristic for each DUT is different from each other. In addition, the test pattern for each DUT could be dynamically determined based on the result by judging pass/fail of the DUT in a test for writing of data.
However, when the general test apparatuses provide the test pattern to each DUT during providing a predetermined test pattern to a plurality of DUTs to test the plurality of DUTs, the test apparatus has to stop providing the test pattern to the DUTs once and set the test pattern by the software for controlling the test apparatus, so that it takes a long time to perform the test.
Thus, the object of the present invention is to provide a test apparatus a test method which are capable of solving the problem accompanying the conventional art. The above and other objects can be achieved by combining the features recited in independent claims. Then, dependent claims define further effective specific example of the present invention.
In order to solve the above described problems, a first aspect of the present invention provides a test apparatus that tests a plurality of device under tests. The test apparatus includes: a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of device under tests; a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of device under tests; an additional pattern storage section that previously stores therein an additional pattern to be added to the common pattern; and an each pattern adding section that reads the additional pattern for each of the device under tests based on a result signal outputted from the device under test and provides the additional pattern added with the common pattern to the device under test.
A second aspect of the present embodiment provides a test method of testing a plurality of device under test by using a test apparatus. The test method includes the steps of: generating a common pattern being the pattern of a test signal common to the plurality of device under tests. The test apparatus whose additional pattern storage section previously stores therein an additional pattern to be added to the common pattern; and reading the additional pattern for each of the device under tests from the additional pattern storage section based on a result signal outputted from each of the device under tests and provides the same added with the common pattern to each of the device under tests.
Here, all necessary features of the present invention are not listed in the summary of the invention. The sub-combinations of the features may become the invention.
According to the present invention, the test apparatus can perform a test by providing a test pattern to each device under test even if a plurality of device under test are tested in parallel.